Field-Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs) have been used in data communication and telecommunication systems. Conventional PLDs and FPGAs consist of an array of digital blocks, with the blocks programmed to implement a function or equation by processing digital signals. Some currently-available Complex PLD (CPLD) products may comprise arrays of logic cells. During placement of an electronic design on such devices, a conventional EDA program (tool) can place the component instances of the design anywhere on the chip because such devices (e.g., FPGAs, PLDs, CPLDs) typically provide connectivity from any digital block to any input-output (IO) pin over substantially symmetric interconnects. Further, since in such devices there are no physical restrictions on where digital block instances and IO instances can be placed, the placer of a conventional EDA program typically tries to find the optimal placement in order to obtain a certain benefit such as the least timing delay or the lowest power consumption.
However, the placers of conventional EDA programs do not work well (if at all) for highly constrained chip architectures that have physical restrictions on the connectivity between digital blocks and IO pins. For example, conventional EDA programs may consume a lot of computing resources (e.g., memory, CPU time, etc.) and may take a long time (or even fail) when trying to find a placement solution for an electronic design on a programmable chip architecture in which the locations of at least some digital blocks are interdependent with the locations of IO pins. This is not the least because the placers in conventional EDA programs treat the placement of IO pins and the placement of digital blocks as separate placement tasks that are performed separately and independently of each other (typically, with IO pins being placed first) and often by using separate placement algorithms.
The above deficiencies of conventional EDA programs with respect to highly constrained chip architectures are exacerbated further since the ever-increasing size and complexity of electronic designs typically lead to less efficient placements, which in turn cause less efficient use of processing resources by the target chips during operation.